1. Field of the Invention
This invention relates to semiconductor device manufacturing, and more particularly, to an improved method for processing a semiconductor topography.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Forming substantially planar surfaces during the processing of a semiconductor topography may involve numerous fabrication steps. For example, a layer may be deposited across a previously patterned layer of a semiconductor topography. Elevational disparities of such a deposited layer may be reduced by planarizing the layer. In some embodiments, an opening or a trench may be formed within a semiconductor topography and subsequently filled with a layer of trench fill material. In this manner, the layer of trench fill material may be formed within the opening and on an upper surface of the semiconductor surface. The layer of trench fill material may then be planarized such that an upper surface of the structure within the trench may be substantially coplanar with an upper surface of the semiconductor topography.
Substantially planar surfaces within a semiconductor topography may play an important role in fabricating overlying layers and structures. For example, step coverage problems may arise when a material is deposited over a surface having raised and recessed regions. Step coverage is defined as a measure of how well a film conforms over an underlying step and is expressed by the ratio of the minimum thickness of a film as it crosses a step to the nominal thickness of the film over horizontal regions. Furthermore, correctly patterning layers upon a surface containing fluctuations in elevation may be difficult using optical lithography. The depth-of-focus of the lithography alignment system may vary depending upon whether the resist resides in an elevational xe2x80x9chillxe2x80x9d or xe2x80x9cvalleyxe2x80x9d area. Furthermore, substantially planar surfaces may become increasingly important as the feature sizes of semiconductor devices are reduced, since the depth of focus required to pattern an upper surface of a topography may increase with reductions in feature size. If a topography is nonplanar, the patterned image may be distorted and the intended structure may not be formed to the specifications of the device.
A technique that is often used to planarize or remove the elevational fluctuations in the surface of a semiconductor topography is chemical mechanical polishing xe2x80x9cCMP.xe2x80x9d A conventional CMP process may involve placing a semiconductor wafer face-down on a polishing pad which lies on or is attached to a table or platen. During the CMP process, the polishing pad and/or the semiconductor wafer may be set into motion as the wafer is forced against the pad. An abrasive, fluid-based chemical suspension, often referred to as a xe2x80x9cslurry,xe2x80x9d may be deposited onto the surface of the polishing pad. The slurry fills the space between the polishing pad and the wafer surface such that a chemical in the slurry may react with the surface material being polished. The rotational movement of the polishing pad relative to the wafer causes abrasive particles entrained within the slurry to physically strip the reacted surface material from the wafer. Therefore, the CMP process may employ a combination of chemical stripping and mechanical polishing to form a planarized surface.
Unfortunately, a CMP process may not form a substantially planar surface across an entire semiconductor topography. For instance, the slurry may react in recessed regions, causing those regions to be excessively etched. Furthermore, the polishing rate of the CMP may be dependent upon the polish characteristics of the topography. In addition, the polishing pad, being somewhat conformal to the surface topography, may deform in response to polishing laterally adjacent layers comprising different polish properties. Therefore, while the removal rate of raised regions of the dielectric may be greater than that of the recessed regions in a typical CMP process, a significant amount of the recessed regions may, unfortunately, undergo removal. This phenomena is known as the xe2x80x9cdishingxe2x80x9d effect and may reduce the degree of planarization that can be achieved by the CMP process. Consequently, the xe2x80x9cdishingxe2x80x9d effect may cause upper surfaces of structures and layers to curve below polished upper surfaces of adjacent structures or layers. For example, the dishing effect resulting from the fabrication of shallow trench isolation regions may be so severe that portions of the isolation regions may extend below the upper surface of the substrate. Consequently, the active regions of the device may not be adequately isolated.
To insure that the upper surfaces of structures and layers are above or coplanar with upper surfaces of adjacent structures and layers, a polish stop layer may be used to terminate the polishing process at an elevation higher than the intended height of the polished structure or layer. The composition of the polish stop layer is such that it polishes much more slowly than the layer above it. In this manner, polishing may be substantially terminated upon exposing the polish stop layer. Thus, layers or structures formed upon the semiconductor topography adjacent to the polish stop layer may also be polished to approximately the same elevation level as the polish stop layer. Silicon nitride is commonly used as a polish stop layer since it is a relatively hard material, particularly compared to silicon dioxide.
As such, a technique used to form shallow trench isolation regions, for example, may include depositing a layer of silicon nitride (xe2x80x9cnitridexe2x80x9d) across an upper surface of a semiconductor substrate. In some cases, a xe2x80x9cpadxe2x80x9d oxide layer may be interposed between the substrate and nitride layer to reduce inherent stresses between nitride and silicon. Portions of the nitride layer and substrate may be etched away to define a trench within the substrate. Fill oxide (e.g., silicon dioxide) may then be deposited into the trench to a level spaced above the upper surface of the nitride layer. The resulting upper surface of the fill oxide includes a recessed region elevationally raised above the trench area. A trench isolation region may then be formed by subjecting the semiconductor topography to a CMP process. The polish rate of the nitride layer is slower than that of the fill oxide and thus, the nitride layer may act as a polish stop layer. Subsequent to the CMP process, the nitride layer may be removed by a nitride strip followed by a selective etch technique to remove the pad oxide.
The problem of the xe2x80x9cdishing effectxe2x80x9d described above is particularly evident during the aforementioned method of forming shallow isolation regions. In addition to the deformation of the polishing pad and the reaction of the slurry in recessed regions of the fill oxide, the xe2x80x9cdishing effectxe2x80x9d may be further augmented by xe2x80x9coverpolishingxe2x80x9d the polish stop layer. In particular, the surface of the polish stop layer may be xe2x80x9coverpolishedxe2x80x9d or polished to a level spaced below the original upper surface of the polish stop layer to ensure that the fill oxide no longer resides above the polish stop layer. Furthermore, the xe2x80x9cdishing effectxe2x80x9d may be dependent on the pattern density of the topography. For example, a topography having relatively wide spaces between the isolation regions may include a large amount of nitride across the lateral portion of the topography, which typically results in a slower polish rate. Alternatively, topographies having relatively narrow spaces between isolation regions may include less nitride across the lateral surface of the semiconductor topography, typically resulting in a faster polish rate. Consequently, a thicker layer of nitride may be needed to compensate for the increase in the polish rate. In an embodiment that includes a varied pattern density (i.e., isolation regions spaced non-uniformly across a semiconductor substrate), portions of the topography with a large of amount of nitride may be etched at a different rate than the portions of the topography with a small amount of nitride. As such, a substantially non-planar surface may result and isolation regions of differing heights may be produced.
Therefore, it may be advantageous to form a polish stop layer having a sufficient thickness such that the xe2x80x9cdishing effectxe2x80x9d does not extend below the uppermost surface of the substrate subsequent to polishing. Typically, the thickness of the polish stop layer in such an embodiment may be greater than approximately 1500 angstroms and possibly greater than approximately 2000 angstroms. Unfortunately, the use of such a relatively thick polish stop layer may create a significant step height between the resulting shallow trench isolation region and adjacent regions upon removal of the polish stop layer. For example, a step height resulting from the use of a relatively thick polish stop layer may have a thickness between approximately 800 angstroms and approximately 1000 angstroms. Unfortunately, such a step height may be significant enough to cause the aforementioned problems associated with non-planar surfaces. xe2x80x9cStep heightxe2x80x9d as used herein refers to the upper portion of a structure that extends above the upper surface of adjacent topography regions.
Accordingly, it would be advantageous to develop a method for planarizing a semiconductor topography to form structures and layers having small and relatively uniform step heights. Such a method may be particularly advantageous during the formation of shallow trench isolation regions.
The problems outlined above may be in large part addressed by a method for processing a semiconductor topography. In particular, a method is provided which includes planarizing structures and/or layers such that step heights of reduced and more uniform height may be formed. Such a method may include polishing an upper layer of a semiconductor topography to expose a first underlying layer. In addition, the method may include etching away remaining portions of the first underlying layer to expose a second underlying layer and subsequently planarizing the topography. In some cases, the method may include forming the upper layer, first underlying layer, and second underlying layer upon a semiconductor layer and in a single process chamber prior to the polishing, etching, and planarizing processes. Alternatively, the method may include forming each of the layers in one or more different process chambers.
Such a method may be particularly advantageous for the formation of shallow trench isolation regions. As such, a method for fabricating shallow trench isolation regions may include forming one or more trenches extending through a stack of at least three layers arranged over a semiconductor substrate. Such a method may further include blanket depositing a dielectric over the trenches and the stack of layers such that the trenches are filled by the dielectric. The dielectric may then be planarized such that upper surfaces of the dielectric remaining within the trenches are coplanar with an upper surface of an adjacent layer of the stack. In some cases, planarizing the dielectric may include removing one or more layers of the stack. Consequently, the method provided herein may produce a semiconductor topography with one or more trench isolation regions arranged within a semiconductor substrate and a plurality of layers arranged laterally adjacent to the trench isolation regions and upon the semiconductor substrate. In some embodiments, the upper surfaces of the trench isolation regions may be above the plurality of layers.
In an embodiment, the method described herein may include polishing an upper layer of a semiconductor topography to expose a first underlying layer. In a preferred embodiment, polishing the upper layer may include removing portions of the upper layer arranged above the upper surface of the first underlying layer. In some cases, polishing the upper layer may further include polishing a portion of the first underlying layer. In such an embodiment, the thickness of the first underlying layer is preferably sufficient to prevent polishing through the first underlying layer. In addition or alternatively, the method may include depositing the upper layer within a trench of the semiconductor topography prior to polishing the upper layer. In such an embodiment, polishing the upper layer may include polishing the upper layer such that remaining portions of the upper layer are laterally confined by sidewalls of the trench. Regardless of the formation of the upper layer, the method may further include etching away remaining portions of the first underlying layer to expose a second underlying layer and subsequently planarizing the topography. In addition or alternatively, the method may include etching the planarized topography such that a third underlying layer is removed. The third underlying layer, in such an embodiment, may be arranged beneath the second underlying layer. In some embodiments, etching the planarized topography may further include removing a portion of the second underlying layer.
A method for fabricating shallow trench isolation regions is also provided herein. Such a method may include forming one or more trenches extending through a stack of at least three layers arranged over a semiconductor substrate. Such a stack of layers may be formed in a single process chamber or one or more different process chambers prior to the formation of the trenches. The method may further include blanket depositing a dielectric over the trenches and the stack of layers such that the trenches are filled by the dielectric. The dielectric may then be planarized such that upper surfaces of the dielectric remaining within the trenches are coplanar with an upper surface of an adjacent layer of the stack In addition, the method may include etching the upper surface of the adjacent layer to expose the semiconductor substrate. In some embodiments, upper portions of the dielectric may extend less than approximately 500 angstroms above the upper surface of the semiconductor substrate subsequent to etching the upper surface. More specifically, the upper portions of the dielectric may extend between approximately 300 angstroms and approximately 500 angstroms above the upper surface of the semiconductor substrate subsequent to etching the upper surface. In either embodiment, the average thicknesses of the upper portions of the dielectric layer extending above the semiconductor substrate and corresponding to each of the trenches may, in some embodiments, differ by less than approximately 10%, or more preferably by less than approximately 5%.
In a preferred embodiment, planarizing may include removing one or more layers of the stack. For example, planarizing may include polishing the dielectric to expose an upper layer of the stack and etching the upper layer to expose an intermediate layer of the stack. In addition, planarizing the dielectric may include polishing the etched topography to expose the upper surface of an adjacent layer of the stack. In a preferred embodiment, subsequently polishing the topography is sufficient to produce a substantially planar surface without dishing portions of the adjacent layer. In some cases, the adjacent layer may include a lower layer of the stack arranged beneath the intermediate layer. Alternatively, the adjacent layer may include the intermediate layer.
Preferably, the stack may include intervening layers of different etching characteristics. In some embodiments, the intermediate layer and the dielectric may include similar etch characteristics. Likewise, the upper layer and lower layer may include similar etch characteristics in some embodiments. In addition or alternatively, the stack may include intervening layers of different polishing characteristics. For example, the upper layer of the stack may include silicon nitride, while the intermediate layer may include silicon dioxide and the lower layer may include silicon nitride. In some embodiments, the thickness of the upper layer may be between approximately 500 angstroms and approximately 1000 angstroms prior to planarizing the dielectric. The thickness of the intermediate layer, for example, may be between approximately 300 angstroms and approximately 700 angstroms prior to planarizing the dielectric. The thickness of the lower layer, on the other hand, may be between approximately 300 angstroms and approximately 500 angstroms prior to planarizing the dielectric.
Consequently, the method as described herein may form a semiconductor topography including one or more trench isolation regions arranged within a semiconductor substrate and a plurality of layers arranged laterally adjacent to the trench isolation regions and upon the semiconductor substrate. In some embodiments, the plurality of layers may include a silicon nitride layer arranged above the semiconductor substrate and a silicon dioxide layer arranged upon the silicon nitride layer. In addition or alternatively, the upper surfaces of the trench isolation regions may be above the plurality of layers. For example, the upper surfaces of the trench isolation regions may be above the plurality of layers by an amount between approximately 300 angstroms and approximately 1000 angstroms. In some embodiments, the trench isolation regions may include two trench isolation regions spaced a first distance from each other. In addition, the trench isolation regions may include a third trench isolation region spaced a second distance from one of the two trench isolation regions. In such an embodiment, the second distance may be greater than the first distance. In addition, such an arrangement of isolation regions may not, in some embodiments, include any trench isolation regions interposed between the third trench isolation region and the one of the two trench isolation regions. In such an embodiment, the upper surfaces of the third trench isolation region may be farther above the plurality of layers than upper surfaces of the two trench isolation regions.
There may be several advantages to forming structures or layers with reduced and more uniform step heights. For example, a substantially planar upper surface of a semiconductor topography may be formed. In this manner, additional structures and layers may be formed within design specifications of the device. Furthermore, step coverage problems and lithography problems may be minimized. As such, patterning distorted structures and layers may be avoided. The method as described herein may also minimize pattern density constraints since the xe2x80x9cdishing effectxe2x80x9d of the polishing process may be reduced. In this manner, shallow trench isolation regions having reduced and more uniform step heights may be formed. Such a formation may be particularly advantageous in patterns of varied densities.